1. Field of the Invention
The present invention relates to a method of selecting a semiconductor device applied to a circuit into which a plurality of semiconductor memory devices such as so-called ROMs, RAMs, etc. are incorporated and a circuit for embodying the same and, more particularly, improvements in a method of selecting one of a plurality of semiconductor memory devices without fail and a circuit for embodying such method.
2. Description of the Related Art
As one example of this kind of circuit in the prior art, there has been a circuit in which, for example, a so-called CPU (Central Processing Unit) and a plurality of ROMs are incorporated and the CPU can make desired one of the ROMs selectively turn into an operative state according to its own operation sequentially so as to read data from the desired ROM.
In FIG. 6, an example of the above circuit in the prior art is shown. Then, a configuration and an operation of the circuit for selecting the semiconductor memory device in the prior art will be explained in brief hereunder.
In this circuit, a predetermined program is carried out by a CPU 1 to execute operation control of respective portions of the circuit (not shown) and data processing. First and second EEPROMs (Electrically Erasable Programmable Read-Only Memories) 2, 3 in which data necessary for execution of the program are stored respectively are connected to the CPU 1. More particularly, a negative logic chip enable input terminal (portion labeled as "/CE" in FIG. 6) of the first EEPROM 2 is connected to a first input/output terminal (portion labeled as "I/O (1)" in FIG. 6) of the CPU 1. Similarly, a negative logic chip enable input terminal (portion labeled as "/CE" in FIG. 6) of the second EEPROM 3 is connected to a second input/output terminal (portion labeled as "I/O (2)" in FIG. 6) of the CPU 1. Respective serial data output terminals (portions labeled as "SOUT" in FIG. 6) of the first and second EEPROMs 2, 3 are connected together and then connected to a data input terminal (portion labeled as "DATA" in F1G. 6) of the CPU 1 such that a data output line can be used commonly.
According to the above configuration, reading of data from the EEPROMs 2, 3 to the CPU 1 can be effected by outputting a so-called chip enable signal as a control signal from the first input/output terminal I/O (1) or the second input/output terminal I/O (2) of the CPU 1 to select desired one of the first and second EEPROMs 2, 3.
Meanwhile, in the above circuit in the prior art, since the chip enable signal which is output from the CPU 1 to the first and second EEPROMs 2, 3 has to be output based on the program executed by the CPU 1, essentially such chip enable signal should be output only to either one of the first and second EEPROMs 2, 3. However, if there is some trouble, i.e., so-called bug in the program, sometimes the chip enable signal has been output simultaneously to both the first and second EEPROMs 2, 3. In this case, since the serial data output terminals SOUT of the first and second EEPROMs 2, 3 are connected together and then connected to the CPU 1, both the first and second EEPROMs 2, 3 are set to their data output states. In the worst case, there has been such a possibility that both the first and second EEPROMs 2, 3 are damaged. As a result, sufficient reliability has not been able to be assured in the above circuit in the prior art.